Circuit Fault & Failure Description Language

In this paper, we aim at formalising an experimental fault and failure description language in order to design a safety verification process for circuits. We would like to extend methods and techniques which check that circuits are design fault free, e.g. they correctly behave in normal mode, in such a way that circuits could be statically verified as well when unexpected failures arise, e.g. in degraded mode. We then model a formal fault and failure description language that suits a tiny language able to design structural configuration of circuits. As we borrow Gordon and Melham\´s "circuits as predicates" paradigm to perform circuit design verification, we shall define fault and failure semantics in terms of "predicates transformers". We choose to take advantage of higher order logic features to realise this goal. Then we are able to build a verification process for safety properties that express the conditions from which circuit behaviour can be proved stable when faults and failures arise.