Design technique of Viterbi decoder in satellite communication

By analyzing the well-known Viterbi algorithm, a Viterbi decoder especially used in satellite communication system is presented. In this paper, the design technique of each part has been discussed. The decoder adopts 4 butterfly units in part- parallel calculation structure with concise interconnection, which is implemented with Xilinx Virtex-II 2V1000- 5BGS575 FPGA (field programmable gate array). The design delays 54 clock periods and costs 501 slices.