Design technique of Viterbi decoder in satellite communication

Author

Ying Li ; Weijun Lu ; Dunshan Yu ; Xing Zhang

Author_Institution

Dept. of Microelectron., Peking Univ., Beijing

fYear

2007

fDate

12-14 Dec. 2007

Firstpage

162

Lastpage

165

Abstract

By analyzing the well-known Viterbi algorithm, a Viterbi decoder especially used in satellite communication system is presented. In this paper, the design technique of each part has been discussed. The decoder adopts 4 butterfly units in part- parallel calculation structure with concise interconnection, which is implemented with Xilinx Virtex-II 2V1000- 5BGS575 FPGA (field programmable gate array). The design delays 54 clock periods and costs 501 slices.

Keywords

Viterbi decoding; field programmable gate arrays; satellite communication; Viterbi decoder design technique; Xilinx Virtex-II 2V1000- 5BGS575 FPGA; butterfly unit; field programmable gate array; part-parallel calculation structure; satellite communication; FPGA; Viterbi decoder; part-parallel; satellite communication;

fLanguage

English

Publisher

iet

Conference_Titel

Wireless, Mobile and Sensor Networks, 2007. (CCWMSN07). IET Conference on

Conference_Location

Shanghai

ISSN

0537-9989

Print_ISBN

978-0-86341-836-5

Type

conf

Filename

4786162

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=485254