A 7-bit, 1.4 GS/s ADC With Offset Drift Suppression Techniques for One-Time Calibration

This paper describes a digitally calibrated 7-bit, 1.4 GS/s flash analog-to-digital converter (ADC) implemented in 45-nm CMOS. The proposed offset drift suppression techniques for dynamic comparator and preamplifier make the ADC robust against environmental variation. As a result, once the ADC is calibrated at power up, no more calibration is necessary, even under VDD or temperature variations. The robustness is theoretically and experimentally verified. A calibration algorithm for doubling the ADC accuracy is also presented. The ADC occupies a small area of 0.085 mm² and dissipates 33.24 mW at 1.4 GS/s from a 1.15 V supply.