Drop Impact Reliability Analysis of 3-D Chip-on-Chip Packaging: Numerical Modeling and Experimental Validation

This paper aims at investigating the drop impact solder interconnect reliability of an advanced ultra-fine-pitch 3-D integrated circuit chip stacking packaging in accordance with JEDEC board-level test specification through finite-element (FE) simulation and experimental testing. To characterize the transient dynamic responses of the package, ANSYS/LS-DYNA incorporated with the Input-G method is applied. To well simulate the mechanical behaviors of the solder interconnects, a strain-rate-dependent elastoplastic Johnson-Cook constitutive model for the Sn3.5Ag solder is applied. In addition, an inverse calculation is carried out to identify the overall structural damping of the dynamic system. Furthermore, a JEDEC-compliant drop tester is used to conduct the drop test, where failure analysis is performed using an optical microscope. Moreover, a simplified Darveaux fatigue life prediction model is constructed based on the calculated strain energy densities at different JEDEC test conditions together with the corresponding drop test data. To demonstrate the validity of the developed fatigue life prediction model, a confirmatory experiment is performed. Finally, parametric FE study incorporated with experimental design is performed to seek a design guideline for enhanced solder interconnect reliability under drop impact. Both the experimental and simulation data reveal that underfill can greatly enhance the drop impact reliability of the solder interconnects. In addition, the cornered interconnects and even package in a one-component configuration would fail earlier than the central ones, with a cohesive fracture in the Sn3.5Ag solder rather than the intermetallic compound (IMC) and its interface. Besides, an increasing IMC thickness reduces the drop impact solder interconnect reliability while enhancing the thermal cycling one.