• DocumentCode
    4886
  • Title

    A Unified Graphics and Vision Processor With a 0.89 /spl mu/W/fps Pose Estimation Engine for Augmented Reality

  • Author

    Jae-Sung Yoon ; Jeong-hyun Kim ; Hyo-Eun Kim ; Won-Young Lee ; Seok-Hoon Kim ; Kyusik Chung ; Jun-Seok Park ; Lee-Sup Kim

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea
  • Volume
    21
  • Issue
    2
  • fYear
    2013
  • fDate
    Feb. 2013
  • Firstpage
    206
  • Lastpage
    216
  • Abstract
    A unified vision and graphics processor with three layers is shown to provide a fast pipeline for augmented reality. In the image-level layer, a 153.6 GOPS massively parallel processing unit with eight SIMD processors, each containing 128 processing elements, performs highly data-parallel operations. In the sub-image layer, a rasterizer and a pixel arranger respectively generate and reduce data-level parallelism. In the descriptor-level layer, a pose estimation engine executes sequential programs. Our processor can provide images for augmented reality at 100 fps, for a power consumption of 413 mW. This is 39% faster than a comparable smartphone implementation. Our chip is fabricated in a 0.18 μm CMOS process and contains 0.95 M gates.
  • Keywords
    CMOS integrated circuits; graphics processing units; parallel processing; CMOS process; GOPS massive parallel processing unit; SIMD processors; augmented reality; data-level parallelism reduction; image-level layer; pose estimation engine; power 413 mW; power consumption; rasterizer; size 0.18 mum; smartphone implementation; unified graphics; vision processor; Augmented reality; Engines; Estimation; Parallel processing; Pipelines; 3-D graphics; augmented reality (AR); pose estimation; vision processor;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2186157
  • Filename
    6156811