A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS

A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino-compatible, CD logic predischarges the output to logic “0” and conditionally makes a transition to logic “1” through the critical-path CLK PMOS transistors for an NMOS transistor network. The constant delay (regardless of the fan-in) feature makes it up to 2× faster than a dynamic logic gate during the D-Q mode for a complex logic such as a two-bit binary comparator. The proposed comparator´s architecture is divided into two stages, where the first stage adapts a novel tree comparator structure specifically designed for static logic to achieve low-power consumption and the second stage utilizes CD logic to realize high performance without sacrificing the overall energy efficiency. At 1-V supply, the proposed comparator´s measured delay is 167 ps, and has an average power and a leakage power of 2.34 mW and 0.06 mW, respectively. At 0.3-pJ iso-energy or 250-ps iso-delay budget, the proposed comparator with CD logic is 20% faster or 17% more energy-efficient compared to a comparator implemented with just the static logic.