Protocol Performance Simulation Mode VI

With the advent of microprocessors, sophisticated communications protocols are being applied in areas which were previously not economically feasible. To an increasing extent, manual evaluation of protocol efficiency is becoming impractical. The same generic microprocessor chips used to implement protocol hardaware can also aid the system designer in the evaluation of protocol performance. This paper presents an overview of a stochastic simulation computer model which was developed to evaluate the performance of a protocol used for high error rate, long delay path (satellite) channels. The lessons learned and benefits achieved from this development can be applied by system designers to other protocol performance simulation efforts.