DocumentCode
491447
Title
Design and Implementation of Real-time Video Compression System Control Framework
Author
Xiaoli, Li ; Chao, Liu ; Qiang, Wang ; Wenrui, Ding
Author_Institution
Sch. of Comput. Sci. & Technol., Beijing Univ. of Aeronaut. & Astronaut., Beijing
Volume
2
fYear
2009
fDate
6-8 Jan. 2009
Firstpage
581
Lastpage
585
Abstract
In order to implement the real-time video compression system, the compression algorithm should be improved and also need a reasonable control framework which brings no additional overhead and efficient to use of the hardware resources. With the perspective of improve the degree of parallelism of the on-chip peripherals and the core, this paper analyzed the disadvantages of the ping-pong buffers pipeline mechanism at first, and then introduced a improved control framework based on dual-core DSP polling control and ping-pong buffers pipeline to avoid that disadvantages. A H.264 based video encoder used this control framework was implemented on the platform of ADSP-BF561, and the experimental results show that the framework can meet the video compression systempsilas real-time capability and reliability requirements by reducing the coding time, falling the frame loss frequency and improving the system´s work efficiency.
Keywords
buffer circuits; data compression; digital signal processing chips; video coding; ADSP-BF561; H.264 based video encoder; dual-core DSP polling control; hardware resources; onchip peripherals; pipeline mechanism; real-time video compression system control framework; Communication system control; Control systems; Digital signal processing; Hardware; Parallel processing; Pipelines; Real time systems; SDRAM; Streaming media; Video compression; Control; Framework; pipeline;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Mobile Computing, 2009. CMC '09. WRI International Conference on
Conference_Location
Yunnan
Print_ISBN
978-0-7695-3501-2
Type
conf
DOI
10.1109/CMC.2009.244
Filename
4797190
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