Voltage Compliant SOI MESFETs for High Linearity RF Front Ends

With the continued scaling of ULSI CMOS, the reduction in supply voltage, V_DD, represents a significant challenge to the RF design engineer. With the voltage swing of an amplifier limited to V_DD/2 or less, the load presented to the drain of the transistor is chosen to be small enough to generate the necessary output power. This in turn requires that the transistor be driven with sufficient gate overdrive (V_gs - V_th) to ensure that enough current can be supplied to the load while maintaining the device in saturation. The large gate overdrive exacerbates the non-linearities that arise from the square-law behavior of the MOSFET, l_D alpha (V_gs - V_th) , leading to gain compression and distortion. Although a number of elegant techniques have been developed to mitigate the distortion due to the high gate over-drive it would be useful to have a device that allowed higher voltage excursions. High voltage MOSFETs such are commonly available but often require additional process steps to be included in the CMOS flow. We have demonstrated that SOI MESFETs can be integrated alongside CMOS with no changes to the process flow. The MESFETs can tolerate high voltage excursions Gt 12V with f_T and f_max in the GHz range, making them ideally suited to high linearity RF applications. Here we present measured results from a nominal 1 GHz SOI MESFET amplifier that confirm the higher linearity that can be achieved by biasing the device at lower gate over-drive.