DocumentCode :
491569
Title :
A Hybridized Linear Prediction Code Speech Synthesizer
Author :
Reilly, Martin T.
Author_Institution :
Research Engineer, Hazeltine Research Labs, Cuba Hill Road, Greenlawn, New York 11740
Volume :
2
fYear :
1986
fDate :
5-9 Oct. 1986
Abstract :
Hazeltine Corporation has developed a hybrid version of a 2400 bps Linear Prediction Code (LPC) speech synthesizer for use in the airborne tactical environment as part of EJS. The unit´s key features include: minimal throughput delay, internal and external LPC frame synchronization capability, automatic Reed-Solomon decoder frame synchronization, data synchronization maintenance, and system control. A Diagnostic Rhyme Test Score of 87 was obtained for the LPC-10 vocoder. The built-in-test (BIT) provides 80 percent fault isolation and detection. The hybrid form of this unit measures 2 inches square and consumes less than 3 (2.2 typical) wattsusing the CMOS version of the TMS32010 digital signal processor, which is part of the TMS320 processor family.
Keywords :
Automatic control; Control systems; Decoding; Delay; Linear predictive coding; Reed-Solomon codes; Speech coding; Speech synthesis; Synthesizers; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Military Communications Conference - Communications-Computers: Teamed for the 90's, 1986. MILCOM 1986. IEEE
Type :
conf
DOI :
10.1109/MILCOM.1986.4805794
Filename :
4805794
Link To Document :
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