Design of multi-thread based scheme in a Flash Translation Layer

Flash memory solid state disks (SSDs) are gaining popularity and replacing hard disk drives (HDDs) in mobile computing systems, such as ultra mobile PCs (UMPCs) and notebook PCs, because of their lower power consumption, faster random access, and higher shock resistance. In this paper, we propose a high-performance flash memory SSD architecture called Hydra that efficiently and effectively translates the inherent parallelism present in multiple flash memory chips into improved storage system performance. In this paper, we have shown that a design of multi-thread based algorithm in a flash translation layer (FTL). We propose a high-performance flash memory SSD scheme that efficiently and effectively translates the inherent parallelism present in multiple flash memory chips into improved storage system performance. The proposed scheme an algorithm specialized for three basic operations (read, write, and erase operation) about flash memory. The proposed scheme uses multi thread that share the same execution code. It also has a prioritized structure consisting of a multi threads, each thread is capable of executing a sequence of each operation (read, write, and erase) at the same time from each memory block which is the set of data to be continued.