Gain-bandwidth adjusting technique of A 36.1 GHz single stage low noise amplifier using 0.13μm CMOS process

This paper demonstrates that inserting a small resistance at the drain of a cascode LNA can be the simplest way of achieving higher bandwidth with only a slight degradation in noise figure. A 36.1 GHz single stage low noise amplifier is designed in 0.13 mum CMOS Process with a simple passive output matching circuit. The circuit is simulated using Cadence Spectre and simulation results show a forward gain (S21) of 11.4 dB at 36.1 GHz with 4.9 GHz Bandwidth. Reverse isolation is less than -24 dB, input-output matchings are -30.36 dB and -27.65 dB respectively. NF of the circuit is around 2.9 dB. Then the circuit is simulated again, this time employing a small resistance at the drain of the cscode LNA, to show that adding a small resistance at the drain of the cascode LNA is the easiest way to increase bandwidth of the circuit without significant sacrifice of noise figure. This single stage LNA consumes only 3.37 mW of power, when driven from a 1.2 V power supply. To the best of the authors knowledge gain-bandwidth adjusting technique of a single stage low noise amplifier operating at such high frequency is yet to be reported.