32nm high K metal gate (HKMG) designs for low power applications

Low power has become a design imperative well beyond the traditionally power averse consumer handheld market. Power constraint is the number one cited issue by semiconductor designers regardless of the application space they are addressing. This trend can only be expected to continue in our quest for greener technologies and continuous demand for smaller form factor with longer battery life. Gate dielectrics have not scaled since 90 nm largely due to the markets refusal to absorb the unavoidable exponential static power consumption such scaling would cause with traditional transistor devices using Polysilicon Oxynitride (Poly/SiON) gates. The innovation of High K metal gate as a replacement for conventional Poly/SiON gate has broken down the scaling barriers providing significant power/performance advantages while allowing geometry shrinks. For the first time we are able to combine gate scaling together with innovations from strain engineering and back end wiring incorporating ultra-low k dielectrics. This talk will focus on the advantages these innovations offer in areas ranging from library elements to full product designs.In this talk, first we will review High K metal gate process in the viewpoint of design. Then, we will discuss a concept to accelerate the benefits of High K metal gate and how to optimize designs through Design Methodology. Finally, we will show the plan to adopt this innovative technology to the next stage mobile product development.