Hybrid architecture of full-search block-matching motion estimation circuit for MPEG-4 encoder

This paper presents the hybrid architecture of full-search block-matching motion estimation circuit for MPEG-4 encoder. The proposed hybrid architecture requires smaller number of clock cycles and circuit resources compared to other approaches. In order to reduce the number of clock cycles, we use several techniques such as data reuse, pipelining and parallel structure. We reduce the circuit resources by the use of partial tree-structure. We described the RTL circuit in Verilog HDL and synthesized the gate-level crcuit using 130 nm standard cel library. The synthesized circuit is composed of 192,772 logic gates and can process 94 D1 (720 times 480) image frame per second.