New address generation scheme for memory-based FFT processor using multiple radix-2 butterflies

This paper proposes a new address generation scheme for a memory-based fast Fourier transform (FFT) processor using multiple radix-2 butterflies and multiple memory banks. By applying the proposed approach, we can increase the performance linearly with the number of butterflies used in the processor without any memory increase or bank conflicts. Specifically, for an N-point FFT processor using maximum of N/2 butterflies, we can achieve N/2 times speedup compared to the conventional memory-based FFT processor using a single butterfly.