DocumentCode
492749
Title
Selective multiplexer-removal algorithm for lowering power consumption of circuits
Author
Shin, Chi-Hoon ; Oh, Myeong-Hoon ; Kim, Young-Woo ; Kim, Sung-Nam ; Kim, Seong-Woon
Author_Institution
Comput. Software & Eng., Univ. of Sci. & Technol. (UST), Daejeon
Volume
02
fYear
2008
fDate
24-25 Nov. 2008
Abstract
In this paper we propose an algorithm about aggressive, but partial removal of multiplexers used for sharing functional units (FUs). By eliminating some multiplexers and duplicating the FU related, the proposed algorithm could be more advantageous for low power circuits than just keeping the multiplexers. To determine whether a removal of a group of multiplexers is beneficial or not, we compared a FU with multiplexers to multiple replications of the FU without any multiplexer under various conditions. Through the experiments, we aggregated information to be used for finding appropriate multiplexers to be extricated from circuit netlist; using the information, we built an automated algorithm to remove particular multiplexers; we applied it to a netlist of 16 bit processor. The processor that is newly generated by the algorithm consumed average about 12% less power than the initial processor.
Keywords
low-power electronics; microprocessor chips; multiplexing equipment; circuit power consumption reduction; functional units; low power circuits; processor; selective multiplexer-removal algorithm; Costs; Design automation; Design methodology; Energy consumption; Logic circuits; Logic design; Multiplexing; Power engineering computing; Software algorithms; Telecommunication computing; design automation; low power; multiplexer;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location
Busan
Print_ISBN
978-1-4244-2598-3
Electronic_ISBN
978-1-4244-2599-0
Type
conf
DOI
10.1109/SOCDC.2008.4815690
Filename
4815690
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