Design of a motion compensation unit for H.264 decoder using 2-dimensional circular register files

H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory and efficient memory management for data reuse is necessary. We propose the architecture of a motion compensation for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and interpolators with dual-channel pipelined processing elements. The processing elements can interpolate integer-, half- and quarter-pixel data. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. The motion compensation unit has dual processing pipelines for luminance and chroma data. We design a motion compensation unit for the baseline profile using Verilog-HDL.