DocumentCode :
492768
Title :
Path delay fault diagnosis using path scoring
Author :
Lim, Yoseop ; Lee, Joohwan ; Kang, Sungho
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul
Volume :
02
fYear :
2008
fDate :
24-25 Nov. 2008
Abstract :
With the increasing complexity of VLSI devices, more complex faults have appeared. The process of locating input-output paths in the chip that caused the delay fault is termed as delay-fault diagnosis. In this paper, we propose a path delay fault diagnosis algorithm using path scoring. The proposed diagnosis algorithm utilizes reasoning-based diagnosis technique and stuck-at fault diagnosis results to improve diagnosis the resolution of delay-fault diagnosis. We propose a path scoring algorithm to increase first-hit-rate (FHR). Experimental results for ISCAS85 and full-scan version of ISCAS89 benchmark circuits prove the accuracy of the proposed algorithm.
Keywords :
VLSI; fault location; fault simulation; logic testing; ISCAS85; ISCAS89; VLSI; fault diagnosis; first-hit-rate; path delay; path scoring; reasoning-based diagnosis technique; stuck-at fault diagnosis; Circuit faults; Circuit testing; Costs; Data mining; Delay; Fault diagnosis; Process design; Production; Timing; Very large scale integration; component; critical path tracing; delay diagnosis; fault model; path delay fault; timing analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-2598-3
Electronic_ISBN :
978-1-4244-2599-0
Type :
conf
DOI :
10.1109/SOCDC.2008.4815718
Filename :
4815718
Link To Document :
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