Encoding of internal states in synthesis and implementation process of automata into FPGAs

Author

Bukowiec, Arkadiusz ; Barkalov, Alexander ; Titarenko, Larysa

Author_Institution

Inst. of Comput. Eng. & Electron., Univ. of Zielona Gora, Gora, Poland

fYear

2009

fDate

24-28 Feb. 2009

Firstpage

199

Lastpage

201

Abstract

The method of synthesis and implementation of Mealy FSMs into FPGAs is proposed. Synthesis is based on the architectural decomposition and multiple encoding of internal states. States are divided into subsets based on a current state and encoded separately in each subset. The state is decoded in the second-level circuit based on the multiple code and the code of a current state. It leads to implementation of FSM in double-level structure where utilization of both, LUTs and memory blocks of FPGA, is applied. It leads to balanced usage of hardware resources of an FPGA device.

Keywords

field programmable gate arrays; finite state machines; table lookup; FPGA device; FSM; architectural decomposition; field programmable gate arrays; finite state machines; hardware resources; internal states; look-up table; multiple encoding; Automata; Circuit synthesis; Combinational circuits; Decoding; Encoding; Field programmable gate arrays; Logic circuits; Logic functions; Programmable logic arrays; Table lookup; Circuit synthesis; Field programmable gate arrays; Finite state machines; Logic design;

fLanguage

English

Publisher

ieee

Conference_Titel

CAD Systems in Microelectronics, 2009. CADSM 2009. 10th International Conference - The Experience of Designing and Application of

Conference_Location

Lviv-Polyana

Print_ISBN

978-966-2191-05-9

Type

conf

Filename

4839804