Title :
Design and estimation of parallel multiplier versions
Author :
Iakovlieva, Inna
Author_Institution :
Yuriy Fedkovych Chernivtsi Nat. Univ., Ukraine
Abstract :
Different versions of high-level synthesis of binary numbers parallel multipliers were considered and their parameters were determined, such as: equipment costs and time delay. The possible scopes of their application were also estimated.
Keywords :
delays; graph theory; mathematics computing; binary numbers parallel multipliers; high-level synthesis; parallel multiplier versions; Concurrent computing; Cost function; Data processing; Delay effects; Delay estimation; Hardware; High level synthesis; Parallel processing; Pipelines; Productivity; high level synthesis; parallel multiplier;
Conference_Titel :
CAD Systems in Microelectronics, 2009. CADSM 2009. 10th International Conference - The Experience of Designing and Application of
Conference_Location :
Lviv-Polyana
Print_ISBN :
978-966-2191-05-9
