DocumentCode :
492883
Title :
Vector-logical approach to diagnosis of SOC components
Author :
Hahanov, Vladimir ; Vasilenko, Vasilina ; Kulbakova, Natalya ; Gharibi, Wajeb
Author_Institution :
Comput. Eng. Fac., Kharkov Nat. Univ. of Radioelectron., Kharkov, Ukraine
fYear :
2009
fDate :
24-28 Feb. 2009
Firstpage :
301
Lastpage :
304
Abstract :
Models and methods of vector-logical diagnosis of SoC functionalities in real time are proposed. Algebra-logical procedures of embedded fault diagnosis by means of DNF synthesis that forms all functionality diagnosis solutions are described. The method is based on use the fault detection table that is result of fault simulation.
Keywords :
fault simulation; system-on-chip; SoC functionalities; algebra-logical procedures; embedded fault diagnosis; fault detection; fault simulation; vector-logical diagnosis; Aggregates; Circuits; Fault detection; Fault diagnosis; Measurement standards; Real time systems; Registers; Standards development; System testing; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
CAD Systems in Microelectronics, 2009. CADSM 2009. 10th International Conference - The Experience of Designing and Application of
Conference_Location :
Lviv-Polyana
Print_ISBN :
978-966-2191-05-9
Type :
conf
Filename :
4839838
Link To Document :
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