Multi-layer on-chip inductor for 10–100 GHz frequency applications

Author

Deevi, B.V.N.S.M. ; Rao, N. Bheema

Author_Institution

Dept. of E.C.E ., Nat. Inst. of Technol. Warangal, Warangal, India

Volume

51

Issue

3

fYear

2015

fDate

2 5 2015

Firstpage

270

Lastpage

272

Abstract

A multi-layer inductor is proposed to achieve high inductance with moderate Q-factor values. The development of integration of devices technology in radio-frequency (RF) has increased the importance of on-chip inductors. In the literature, the planar inductor, the three-dimensional (3D) inductor with constant width and the 3D inductor with variable width are reported. Using the basic concept of multi-layer technology in very large-scale integration (VLSI) system design and considering lambda rules, the proposed inductor is designed. The inductance of the proposed inductor is nearly 37-45% higher compared with reported inductors with a moderate quality factor. This inductor is realised using 180 nm scale technology with an area of cross-section 10 × 10 μm². Results are presented using the IE3D EM field solver with the help of series RL and shunt RC lumped Pi model.

Keywords

Q-factor; RC circuits; VLSI; inductors; integrated circuit design; microwave integrated circuits; millimetre wave integrated circuits; 3D inductor; IE3D EM field solver; RF technology; VLSI system; frequency 10 GHz to 100 GHz; lambda rules; moderate q-factor value; multilayer on-chip inductor; planar inductor; quality factor; radiofrequency technology; series RL lumped Pi model; shunt RC lumped Pi model; size 180 nm; three-dimensional inductor; very large-scale integration system;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2014.3202

Filename

7029804