Title :
Design of Multi-phase Clock Generation and Selection Circuit for CDR
Author :
Junyong, Deng ; Lin, Jiang ; Zecang, Zeng
Author_Institution :
Comput. Dept., Xi´´an Inst. of Post & Telecommun., Xi´´an, China
fDate :
March 31 2009-April 2 2009
Abstract :
This paper describes the principle with the quadrature reference clocks in dual-loop clock and data recovery circuit. The traditional scheme of generating quadrature clock is analyzed, and a new algorithm with phase interpolation and selection is presented after the modification of the circuit in existence. This algorithm enhances the jitter tolerance of input datum. The scheme is realized with CMOS circuit, as well as the entire circuit is simulated with Cadence Spectre in 0.18 um CMOS technology.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; integrated circuit design; CMOS circuit design; dual-loop clock; jitter tolerance; multiphase clock generation; phase interpolation; quadrature reference clock; selection circuit; size 0.18 mum; CMOS technology; Circuits; Clocks; Computer science; Energy consumption; Interpolation; Jitter; Phase locked loops; Power generation; Sampling methods;
Conference_Titel :
Computer Science and Information Engineering, 2009 WRI World Congress on
Conference_Location :
Los Angeles, CA
Print_ISBN :
978-0-7695-3507-4
DOI :
10.1109/CSIE.2009.459
