Single-Phase Adiabatic Tree Multipliers with Modified Booth Algorithm

This paper presents an adiabatic tree multiplier based on modified Booth algorithm, which operates in a single-phase power-clock. All circuits are realized using improved CAL (clocked adiabatic logic) circuits with TSMC 0.18 mum CMOS process. The proposed single-phase adiabatic booth encoder attains energy savings of 82% at 50 MHz and 70% at 300 MHz, compared with its CMOS counterpart. The single-phase adiabatic partial product generator and 4-2 compressors based on the gate level attain energy savings of 80% and 76% as compared to the conventional CMOS implementations at 200 MHz, respectively.