The Implementation of Low-Power CAM with Fully Adiabatic Driving for Large Node Capacitances

An adiabatic 32 times 32 content-addressable memory (CAM) are designed in this paper, which consists of a CAM storage-cell array, address decoders, bit-lines drivers, and match-line driving circuits. All circuits except for CAM storage cells and driving control circuits for match lines are realized using CPAL (complementary pass-transistor adiabatic logic) circuits. The charge of large node capacitances on match lines, bit lines, word lines, and address lines is well recovered in fully adiabatic manner. For comparison, a conventional 32 times 32 CAM is also implemented using the similar structure. The two CAM cores have been integrated in a test chip with Chartered 0.35 mum CMOS process. Based on the post-layout simulations, the adiabatic CAM can work very well, and it attains about 86% energy saves compared to the conventional CMOS implementation at 100 MHz.