Title :
The Implementation of Low-Power CAM with Fully Adiabatic Driving for Large Node Capacitances
Author :
Xu, Qingbo ; Ye, Lifang ; Hu, Jianping ; Huang, Lijun
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
fDate :
March 31 2009-April 2 2009
Abstract :
An adiabatic 32 times 32 content-addressable memory (CAM) are designed in this paper, which consists of a CAM storage-cell array, address decoders, bit-lines drivers, and match-line driving circuits. All circuits except for CAM storage cells and driving control circuits for match lines are realized using CPAL (complementary pass-transistor adiabatic logic) circuits. The charge of large node capacitances on match lines, bit lines, word lines, and address lines is well recovered in fully adiabatic manner. For comparison, a conventional 32 times 32 CAM is also implemented using the similar structure. The two CAM cores have been integrated in a test chip with Chartered 0.35 mum CMOS process. Based on the post-layout simulations, the adiabatic CAM can work very well, and it attains about 86% energy saves compared to the conventional CMOS implementation at 100 MHz.
Keywords :
CMOS memory circuits; content-addressable storage; logic design; low-power electronics; CMOS process; address decoders; adiabatic content-addressable memory design; bit-lines drivers; complementary pass-transistor adiabatic logic circuits; frequency 100 MHz; low-power CAM; match-line driving circuits; post-layout simulation; size 0.35 mum; storage-cell array; CADCAM; CMOS logic circuits; CMOS process; Capacitance; Circuit simulation; Circuit testing; Computer aided manufacturing; Energy consumption; Energy loss; Logic circuits; Adiabatic circuits; Content-addressable memories; Low power;
Conference_Titel :
Computer Science and Information Engineering, 2009 WRI World Congress on
Conference_Location :
Los Angeles, CA
Print_ISBN :
978-0-7695-3507-4
DOI :
10.1109/CSIE.2009.894
