Title :
Design Methods of Multi-DSP Parallel Processing System
Author :
Wu, Wei ; Wang, Jun ; Li, Wei ; Zhang, Wenhao
Author_Institution :
Sch. of Electron. & Inf. Eng., Beihang Univ., Beijing, China
fDate :
March 31 2009-April 2 2009
Abstract :
In this paper, the cascaded topology of Multi-Digital Signal Processor (DSP) parallel processing system is presented, and the common architecture for multi-DSP parallel systems is summarized. In addition, according to the features of Field Programmable Gate Array (FPGA) and DSP, a parallel system based on 2-level bus structure has been proposed. Two parallel systems, respectively based on TMS320C641x and TS201, have been realized too. Having compared their advantages and performances, we finally conclude the design methods of multi-DSP parallel processing system.
Keywords :
digital signal processing chips; field buses; field programmable gate arrays; logic design; network topology; parallel architectures; 2-level bus structure; FPGA; cascaded topology; field programmable gate array; multi DSP parallel processing system; parallel architecture; single chip design method; Data communication; Design methodology; Digital signal processing; Digital signal processing chips; Field programmable gate arrays; Parallel processing; Radar signal processing; Real time systems; Signal processing; Topology; Parallel processing; hardware architecture; multi-DSP; real-time processing;
Conference_Titel :
Computer Science and Information Engineering, 2009 WRI World Congress on
Conference_Location :
Los Angeles, CA
Print_ISBN :
978-0-7695-3507-4
DOI :
10.1109/CSIE.2009.40
