The design of high performance dual modulus divider-by Prescaler

In this paper, a novel design plan of divider was presented. In the higher frequency band, M/S DFF structured by CMOS SCL were used to divide to satisfy the high-speed command; in the lower frequency band, DFF with self-latch function were used. This structure not only has locked function but also has less MOS transistors than M/S DFF. So it satisfies the command of lower power and noise. The whole system could realize high-speed, low power, and low-jitter. The circuit was simulated by Cadence Spectre under the CMOS technology of TSMC 0.18um. It was shown that the highest frequency of the divider is up to 5GHz. When T=27 °, VDD=1.8V, f=5GHz, the power consumption of the circuit was only 4.32mW(1.8V×2.4mA).