Title :
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process
Author :
Shien-Yang Wu ; Liaw, J.J. ; Lin, C.Y. ; Chiang, M.C. ; Yang, C.K. ; Cheng, J.Y. ; Tsai, M.H. ; Liu, M.Y. ; Wu, Shien-Yang ; Chang, C.H. ; Hu, L.C. ; Lin, C.I. ; Chen, H.F. ; Chang, S.Y. ; Wang, S.H. ; Tong, P.Y. ; Hsieh, Y.L. ; Pan, K.H. ; Hsieh, C.H. ;
Author_Institution :
Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
Abstract :
For the first time, we present good yielding 64 Mb SRAM test-chip with the smallest cell using dual/triple gate oxide process flow in 28 nm node. The low power technology platform continues scaling trend and extends SiON/poly technology beyond 32 nm node with gate density of 2.3times higher than that of 45 nm, and integrates high density (0.127 um2) and low Vccmin (0.155 um2) 6-T SRAM cells, low power transistors, analog/RF components and Cu-low-k interconnect. Simultaneously available low standby (LSTP) and low operating power (LOP) transistors provide 25-40% speed improvement or 30-50% active power reduction over prior 45 nm technology. Competitive mismatch (AVt of 2.86 mV.um) and 1/f noise characteristics, and enhanced MOM unit capacitance of 4.4 fF/um2 (4 metal layers) with Q factor >100 at 2.4 GHz are also achieved.
Keywords :
1/f noise; CMOS memory circuits; SRAM chips; capacitance; integrated circuit interconnections; low-power electronics; system-on-chip; 1/f noise; CMOS low power platform technology; Cu-low-k interconnect; Q factor; SRAM test-chip; active power reduction; analog RF components; digital RF components; dual gate oxide process flow; enhanced MOM unit capacitance; frequency 2.4 GHz; gate density; low operating power transistors; low standby transistors; memory size 64 MByte; size 28 nm; speed improvement; triple gate oxide SOC technology; triple gate oxide process flow; CMOS process; CMOS technology; Capacitance; Manufacturing processes; Message-oriented middleware; Power transistors; Q factor; Radio frequency; Random access memory; Testing;
Conference_Titel :
VLSI Technology, 2009 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-3308-7
