High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface

Author

Shimojo, Yoshiro ; Konno, Atsushi ; Nishimura, Jun ; Okada, Takayuki ; Yamada, Yuki ; Kitazaki, Soichiro ; Furuhashi, Hironobu ; Yamazaki, Soichi ; Yahashi, Katsunori ; Tomioka, Kazuhiro ; Minami, Yoshihiro ; Kanaya, Hiroyuki ; Shuto, Susumu ; Yamakawa, K

Author_Institution

Semicond. Co., Toshiba Corp., Yokohama, Japan

fYear

2009

fDate

16-18 June 2009

Firstpage

218

Lastpage

219

Abstract

Novel cell technologies are successfully developed for the world´s highest-density and highest-speed 128 Mb chain FeRAMtrade with SDRAM-compatible 1.6 GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout with triangular capacitors, advanced nestled chain structure, high-density cover film and low-damage etching technique are established. New architecture with small bit line capacitance of 60 fF is also installed. With these new technologies, the cell signal window reaches 380 mV, which is sufficient for stable 128 Mb 1T1C operation.

Keywords

CMOS memory circuits; etching; ferroelectric capacitors; ferroelectric storage; random-access storage; 1T1C operation; CMOS technologies; SDRAM-compatible DDR2 interface; advanced nestled chain structure; byte rate 1.6 GByte/s; capacitance 60 fF; capacitor shrinkage; ferroelectric memory; half-pitch layout; high-density cover film; highest-density chain FeRAM; highest-speed chain FeRAM; low-damage etching technique; memory size 128 MByte; signal window reduction; triangular capacitors; voltage 380 mV; CMOS technology; Capacitance; Capacitors; Degradation; Etching; Ferroelectric films; Ferroelectric materials; Hydrogen; Nonvolatile memory; Random access memory; 128Mb; Chain and hydrogen barrier; FeRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2009 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-3308-7

Type

conf

Filename

5200605