DocumentCode
497169
Title
Parallel multi-confined (PMC) cell technology for high density MLC PRAM
Author
Oh, G.H. ; Park, Y.L. ; Lee, J.I. ; Im, D.H. ; Bae, J.S. ; Kim, D.H. ; Ahn, D.H. ; Horii, H. ; Park, S.O. ; Yoon, H.S. ; Park, I.S. ; Ko, Y.S. ; Chung, U-in ; Moon, J.T.
Author_Institution
Semicond. R&D Div., Samsung Electron. Co., Ltd., Yongin, South Korea
fYear
2009
fDate
16-18 June 2009
Firstpage
220
Lastpage
221
Abstract
We first present a parallel multi-confined (PMC) cell structure on single contact was successfully integrated by using CVD PCM process. PMC cell shows the discrete four resistance levels with increasing applied current, and its middle resistances (D01, D10) have the low drift coefficient under 0.007. The four resistance levels were maintained up to 2E5 cycles. From simulation results, PMC cell structure is applicable to MLC PRAM device below 25nm design rule.
Keywords
cells (electric); chemical vapour deposition; concurrency theory; CVD PCM process; high-density MLC PRAM; parallel multiconfined cell technology; Amorphous materials; Crystallization; Dielectrics; Electrodes; Lithography; Phase change materials; Phase change random access memory; Thermal resistance; Very large scale integration; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2009 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-3308-7
Type
conf
Filename
5200606
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