• DocumentCode
    497171
  • Title

    A novel buried-channel FinFET BE-SONOS NAND Flash with improved memory window and cycling endurance

  • Author

    Lue, Hang-Ting ; Hsiao, Yi-Hsuan ; Du, Pei-Ying ; Lai, Sheng-Chih ; Tzu-Hsuan Hsu ; Hong, S.P. ; Wu, M.T. ; Hsu, F.H. ; Lien, N.Z. ; Lu, Chi-Pin ; Hsieh, Jung-Yu ; Yang, Ling-Wu ; Yang, Tahone ; Chen, Kuang-Chao ; Hsieh, Kuang-Yeu ; Liu, Rich ; Lu, Chih-Y

  • Author_Institution
    Emerging Central Lab., Macronix Int. Co., Ltd., Hsinchu, Taiwan
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    224
  • Lastpage
    225
  • Abstract
    In NAND flash, devices are normally erased to negative Vt and then programmed to positive Vt. In this work we introduce a novel depletion-mode (normally on) buried-channel, junction-free n-channel NAND flash device. The buried-channel NAND flash shifts the P/E Vt ranges below those for the conventional surface-channel device, and is more suitable for the NAND Flash memory design. Due to the lower initial Vt, the device shows faster erase speed and higher immunity to read disturb. Furthermore, the buried-channel device has significantly improved cycling endurance, because the buried channel is insensitive to the interface state (Dit) generation during program/erase stressing. A lightly doped shallow n-type channel serves both as the buried bit line and as the source/drain of the junction-free structure. The short channel effects are overcome by using FinFET. The buried-channel NAND flash uses a simple program-inhibit method by directly raising the buried bit line potential without introducing a deep depletion in the conventional self-boosting method. A successful sub-30 nm buried-channel FinFET BE-SONOS NAND flash with MLC is demonstrated.
  • Keywords
    MOSFET; NAND circuits; flash memories; buried-channel FinFET BE-SONOS NAND flash memory; cycling endurance; depletion mode buried channel; interface state generation; junction-free n-channel NAND flash device; memory window; program-erase stressing; self-boosting method; surface channel device; Degradation; Doping profiles; Electronic mail; Electrons; FinFETs; Interface states; Neck; Stress control; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2009 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-3308-7
  • Type

    conf

  • Filename
    5200608