DocumentCode :
49718
Title :
LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing
Author :
Yamato, Yuta ; Miyase, Kohei ; Kajihara, Seiji ; Xiaoqing Wen ; Laung-Terng Wang ; Kochte, Michael A.
Author_Institution :
Nara Inst. of Sci. & Technol., Nara, Japan
Volume :
30
Issue :
4
fYear :
2013
fDate :
Aug. 2013
Firstpage :
60
Lastpage :
70
Abstract :
In this contribution, the authors describe a method for ensuring that false failures do not occur when shifting scan chains for testing. Their approach identifies an optimal combination of scan segments for simultaneous clocking that reduces the switching activity near clock trees while maintaining the average power reduction for conventional scan segmentation. Experiments using various benchmark circuits demonstrate the overall utility of their approach.
Keywords :
clocks; timing circuits; LCTI SS; average power reduction; avoiding shift timing failures; benchmark circuits; clock trees; low clock tree impact scan segmentation; optimal combination; scan segments; scan testing; shifting scan chains; simultaneous clocking; switching activity; Clocks; Failure analysis; Logic gates; Power consumption; Software testing; Synchronization; Timing analysis; clock skew; clock tree; scan segmentation; scan testing; shift power reduction; switching activity;
fLanguage :
English
Journal_Title :
Design & Test, IEEE
Publisher :
ieee
ISSN :
2168-2356
Type :
jour
DOI :
10.1109/MDT.2012.2221152
Filename :
6319363
Link To Document :
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