DocumentCode
497188
Title
Cost-Effective 28-nm LSTP CMOS using gate-first metal gate/high-k technology
Author
Tomimatsu, T. ; Goto, Y. ; Kato, H. ; Amma, M. ; Igarashi, M. ; Kusakabe, Y. ; Takeuchi, M. ; Ohbayashi, S. ; Sakashita, S. ; Kawahara, T. ; Mizutani, M. ; Inoue, M. ; Sawada, M. ; Kawasaki, Y. ; Yamanari, S. ; Miyagawa, Y. ; Takeshima, Y. ; Yamamoto, Y.
Author_Institution
Production Technol. Dev. Unit, Renesas Technol. Corp., Itami, Japan
fYear
2009
fDate
16-18 June 2009
Firstpage
36
Lastpage
37
Abstract
Metal gate/high-k CMOS technology for 28-nm node low power and low standby power application is demonstrated. A gate-first single metal/high-k gate stack has been employed together with leading-edge isolation, ultra-shallow junction, and stress engineering technologies. High density and high performance device is provided with least process cost increase.
Keywords
CMOS integrated circuits; integrated circuit design; isolation technology; low-power electronics; CMOS technology; gate-first metal gate/high-k technology; leading-edge isolation; size 28 mm; stress engineering; CMOS technology; High K dielectric materials; High-K gate dielectrics; Intrusion detection; Isolation technology; Leakage current; MOS devices; MOSFETs; Stress; Surface-mount technology;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2009 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-3308-7
Type
conf
Filename
5200625
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