Title :
Impact of area scaling on threshold voltage lowering in La-containing high-k/metal gate NMOSFETs fabricated on (100) and (110)Si
Author :
Inoue, M. ; Satoh, Y. ; Kadoshima, M. ; Sakashita, S. ; Kawahara, T. ; Anma, M. ; Nakagawa, R. ; Umeda, H. ; Matsuyama, S. ; Fujimoto, H. ; Miyatake, H.
Author_Institution :
Renesas Technol. Corp., Itami, Japan
Abstract :
Impact of area scaling (especially narrow channel) on Vt lowering by La incorporation in high-k gate NMOSFETs is reported for the first time. It is clarified that Vt becomes higher in narrower channel for La-containing high-k gate. Efforts are made to ascribe the strong dependence of Vt on gate width to less effectiveness of La compared to wider channel. Influence of channel orientation at STI edge is focused on to explain this phenomenon. It is presented that excellent narrow channel characteristic can be obtained using proper La-amount range and improved annealing process.
Keywords :
MOSFET; annealing; hafnium compounds; high-k dielectric thin films; lanthanum; HfJk:La; Si; annealing process; channel orientation; gate width; high-k gate NMOSFET; narrow channel characteristic; threshold voltage; Annealing; Controllability; Fabrication; High K dielectric materials; High-K gate dielectrics; MOS devices; MOSFETs; Threshold voltage; Visualization;
Conference_Titel :
VLSI Technology, 2009 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-3308-7
