Title :
New 3D integration technology and 3D system LSIs
Author :
Koyanagi, Mitsumasa
Author_Institution :
Dept. of Bioeng. & Robot., Tohoku Univ., Sendai, Japan
Abstract :
A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding has been developed. Various kinds of 3-D LSI test chips such as 3-D microprocessor chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology called super-chip integration based on the reconfigured wafer- to-wafer bonding in which the reconfigured wafers are produced by simultaneously aligning and bonding more than one thousand of known good dies (KGD´s) on a supporting wafer using a self-assembly technique.
Keywords :
large scale integration; microprocessor chips; self-assembly; wafer bonding; 3-D LSI test chips; 3-D microprocessor chip; reconfigured wafer-to-wafer bonding; self-assembly technique; super-chip integration; three-dimensional integration technology; through silicon vias; Cache memory; Capacitance; Circuit testing; Energy consumption; Large scale integration; Microprocessor chips; Silicon; Through-silicon vias; Wafer bonding; Wiring; 3D LSI; TSV; super chip; wafer bonding;
Conference_Titel :
VLSI Technology, 2009 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-3308-7
