Author_Institution :
SEMATECH, Albany, NY, USA
Abstract :
3D interconnect technology using through silicon vias (TSVs) has been investigated for several years now [1-3]; in the last few years, it has begun to gain industry-wide attention. Considerable effort has been put into defining clear product drivers, narrowing and focusing the multitude of technology options [4], and increasing attention to cost implications [5]. Simultaneously, the conventional scaling of semiconductors is being challenged by rapidly increasing complexity at each node. This is drawing 3D towards the spotlight. The process technologies unique to 3D (TSV reactive ion etch [RIE], bonding, and thinning) have demonstrated considerable improvements in capability over the last few years, and the first CMOS products have recently been announced [6]. This presentation will cover different aspects of 3D ICs, including process and integration technologies, metrology, cost modeling, and roadmaps and standards and present leading edge results from SEMATECH´s 300 mm via-mid copper-to-copper 3D IC program.
Keywords :
elemental semiconductors; integrated circuit design; integrated circuit measurement; integrated circuit modelling; silicon; 3D interconnect technology; SEMATECH; Si; cost modeling; high volume manufacturing; integration technology; metrology; roadmaps; standards; through silicon vias; via-mid copper-to-copper 3D IC program; Bonding; CMOS process; CMOS technology; Costs; Etching; Integrated circuit modeling; Manufacturing industries; Metrology; Silicon; Through-silicon vias; 3D interconnects; 3D metrology; TSV; cost modeling; through silicon vias;
