Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate

Author

Li, Ming ; Yeo, Kyoung Hwan ; Sung Dae Suk ; Yeoh, Yun Young ; Kim, Dong-Won ; Chung, Tae Young ; Oh, Kyung Seok ; Lee, Won-Seong

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin, South Korea

fYear

2009

fDate

16-18 June 2009

Firstpage

94

Lastpage

95

Abstract

In this paper, sub-10 nm gate-all-around (GAA) CMOS silicon nanowire field-effect transistors (SNWFET) on bulk Si substrate are fabricated successfully for the first time with 13-nm-diameter silicon nanowire channel. On-state currents of 1494/1054 muA/mum at off leakage currents of 102/6.44 nA/mum are obtained for N/PMOS, respectively. The impacts of nanowire diameter (D_NW) and gate oxide thickness (T_OX) as well S/D parasitic resistance (R_SD) on performance are investigated in details.

Keywords

CMOS integrated circuits; MOSFET; leakage currents; nanoelectronics; nanowires; N-PMOS; SNWFET; gate-all-around CMOS nanowire field-effect transistor; off leakage current; silicon nanowire channel; size 13 nm; Ballistic transport; CMOS technology; FETs; Leakage current; MOS devices; Research and development; Scalability; Silicon; Substrates; Transistors; CMOS; ballistic transport; gate-all-around; nanowire; source-drain parasitic resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2009 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-3308-7

Type

conf

Filename

5200646