Author :
Greene, B. ; Liang, Q. ; Amarnath, K. ; Wang, Y. ; Schaeffer, Jonathan ; Cai, M. ; Liang, Y. ; Saroop, S. ; Cheng, J. ; Rotondaro, A. ; Han, S.-J. ; Mo, R. ; McStay, K. ; Ku, S. ; Pal, R. ; Kumar, M. ; Dirahoui, B. ; Yang, B. ; Tamweber, F. ; Lee, W.-H. ;
Author_Institution :
IBM Syst. & Technol. Group, IBM Semicond. R&D Center (SRDC), Hopewell Junction, NY, USA
Abstract :
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by high-k/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. AC drive currents of 1.55 mA/um and 1.22 mA/um have been achieved at an off-state of 100 nA/mum and VDD of 1 V for NFET and PFET, respectively. For the first time, we have also demonstrated that SOI maintains performance benefit over bulk silicon in high-k/metal gate and 32 nm ground rules.
Keywords :
CMOS memory circuits; Ge-Si alloys; SRAM chips; copper; high-k dielectric thin films; immersion lithography; low-k dielectric thin films; semiconductor materials; silicon-on-insulator; AC drive currents; Cu; NFET; PFET; SOI CMOS technology; SRAM array test vehicle; SRAM cell; SiGe; aggressive ground rules; dual stress liner; gate capacitance; high-k/metal gate electrodes; immersion lithography; size 25 nm; size 32 nm; storage capacity 16 Mbit; strained silicon elements; ultralow-k back end; voltage 0.6 V; voltage 1 V; wavelength 193 nm; CMOS technology; Germanium silicon alloys; High K dielectric materials; High-K gate dielectrics; Lithography; Random access memory; Silicon germanium; Technological innovation; Testing; Vehicles;
