• DocumentCode
    497229
  • Title

    Comprehensive design methodology of dopant profile to suppress gate-LER-induced threshold voltage variability in 20nm NMOSFETs

  • Author

    Fukutome, H. ; Hori, Y. ; Sponton, L. ; Hosaka, K. ; Momiyama, Y. ; Satoh, S. ; Gull, R. ; Fichtner, W. ; Sugii, T.

  • Author_Institution
    Fujitsu Microelectron. Ltd., Akiruno, Japan
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    146
  • Lastpage
    147
  • Abstract
    We have demonstrated for the first time that parallel extension implantation tilted along the gate width direction enables to reduce the threshold voltage (Vth) fluctuation in nMOSFETs at high Vd by 15%. We have clarified by direct carrier profiling and 3D simulation that the parallel implantation makes lateral extension edge smooth (less roughness induced by gate LER). Thanks to reduced fluctuation in effective channel length, we have made it possible to operate 20-nm nMOSFETs with the Vth variability as much as pMOSFETs have.
  • Keywords
    MOSFET; doping profiles; nanoelectronics; 3D simulation; NMOSFET; design methodology; direct carrier profiling; dopant profile; gate-LER-induced threshold voltage variability; parallel extension implantation; size 20 nm; Capacitance; Design methodology; Electronic mail; Fluctuations; Laboratories; MOSFETs; Microelectronics; Smoothing methods; Threshold voltage; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2009 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-3308-7
  • Type

    conf

  • Filename
    5200666
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497229