• DocumentCode
    497231
  • Title

    Low voltage (Vdd∼0.6 V) SRAM operation achieved by reduced threshold voltage variability in SOTB (silicon on thin BOX)

  • Author

    Tsuchiya, Ryuta ; Sugii, Nobuyuki ; Ishigaki, Takashi ; Morita, Yusuke ; Yoshimoto, Hiroyuki ; Torii, Kazuyoshi ; Kimura, Shin´ichiro

  • Author_Institution
    Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    150
  • Lastpage
    151
  • Abstract
    We have successfully demonstrated ldquosilicon on thin BOXrdquo (SOTB) 6T-SRAM with a 50-nm gate. By employing an ultra low-dose channel, this SOTB achieves small Vth variability. As a result, the SOTB SRAM technology has been successfully developed with 0.142 V of static noise margin at Vdd=0.6 V and Vdd_min of 0.63 V because of its excellent Vth variability characteristics. We also show that SOTB CMOS exhibits superior reliability and noise performance. These characteristics indicate robust properties for future industrial high performance and low power LSIs.
  • Keywords
    CMOS integrated circuits; SRAM chips; elemental semiconductors; integrated circuit reliability; large scale integration; low-power electronics; silicon; CMOS; LSI; SRAM; silicon on thin BOX; size 50 nm; threshold voltage variability; voltage 0.142 V; voltage 0.6 V; voltage 0.63 V; CMOS technology; Driver circuits; Laboratories; Low voltage; MOS devices; Noise robustness; Random access memory; Silicon; Subthreshold current; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2009 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-3308-7
  • Type

    conf

  • Filename
    5200668