Author :
Scott, J.C. ; Gluschenkov, O. ; Goplen, B. ; Landis, H. ; Nowak, E. ; Clougherty, F. ; Mocuta, A. ; Hook, T. ; Zamdmer, N. ; Lai, C.W. ; Eller, M. ; Chidambarrao, D. ; Yu, J. ; Chang, P. ; Ferris, J. ; Deshpande, S. ; Li, Y. ; Shang, H. ; Hefferon, G. ; D
Author_Institution :
IBM Almaden Res. Center, San Jose, CA, USA
Abstract :
Unique hybrid approach employing both model-based layout optimization and process improvement was successfully developed for reducing rapid thermal anneal (RTA) driven intra die variations. It has been applied to multiple bulk and SOI designs. The model developed herein enables fast estimation of broad-band reflectance of a random layout in 65 nm, 45 nm, and 32 nm nodes and guides reflectance leveling in the post-design phase. This approach significantly reduces RTA-driven variations showing 30% reduction in intra die ring oscillator range in high-performance products.
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit optimisation; integrated circuit layout; rapid thermal annealing; reflectivity; silicon-on-insulator; ASIC; CMOS; RTA-driven intra-die variation; SOI design; broadband reflectance; intra die ring oscillator; model-based layout optimization; process improvement; rapid thermal anneal; reflectance leveling; size 32 nm; size 45 nm; size 65 nm; Paper technology; Very large scale integration; ASIC; CMOS; DFM; RTA; Reflectance; Reflectivity; Variation;
