GeOI and SOI 3D monolithic cell integrations for high density applications

Author

Batude, P. ; Vinet, M. ; Pouydebasque, A. ; Le Royer, C. ; Previtali, B. ; Tabone, C. ; Clavelier, L. ; Michaud, S. ; Valentian, A. ; Thomas, O. ; Rozeau, O. ; Coudrain, P. ; Leyris, C. ; Romanjek, K. ; Garros, X. ; Sanchez, L. ; Baud, L. ; Roman, A. ; Ca

Author_Institution

LETI, CEA, Grenoble, France

fYear

2009

fDate

16-18 June 2009

Firstpage

166

Lastpage

167

Abstract

In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600degC) of the top GeOI and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect control down to L_G = 50 nm. Both gains in density and performance have been studied with advanced design rules. Processing CMOS on each layer leads to an average 40% density improvement as compared to 2D standard layout.

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; germanium; monolithic integrated circuits; silicon; wafer bonding; CMOS processing; Ge; GeOI 3D monolithic cell integration; GeOI MOSFET; SOI 3D monolithic cell integration; SOI MOSFET; Si; high density applications; process temperature; short channel effect; wafer bonding; CMOS process; Crystallization; FETs; MOSFETs; Performance gain; Temperature control; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2009 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-3308-7

Type

conf

Filename

5200674