Title :
ERSFQ 8-Bit Parallel Adders as a Process Benchmark
Author :
Kirichenko, A.F. ; Vernik, Igor V. ; Vivalda, John A. ; Hunt, Rick T. ; Yohannes, Daniel T.
Author_Institution :
HYPRES, Elmsford, NY, USA
Abstract :
We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES´s 1.0-μm 4-layer 4.5 kA/cm2 process, HYPRES´s 0.25-μm 4-layer 4.5 kA/cm2 process, HYPRES´s 0.25-μm 6-layer 4.5 kA/cm2 planarized process, and MIT Lincoln Lab´s 0.25-μm 4-layer 10 kA/cm2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.
Keywords :
adders; energy conservation; integrated circuit design; integrated circuit manufacture; integrated circuit testing; large scale integration; logic design; logic testing; low-power electronics; ERSFQ; HYPRES planarized process; LSI fabrication process; MIT Lincoln Lab process; RSFQ logic; energy-efficient rapid single flux quantum logic; parallel adders; single flux quantum circuits; size 0.25 mum; size 1.0 mum; Adders; Benchmark testing; Clocks; Computer architecture; Current measurement; Fabrication; Power dissipation; Benchmarking; HPC; RSFQ; benchmarking; zero static power dissipation;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
DOI :
10.1109/TASC.2014.2371875
