A novel on chip circuit for fault detection in digital to analog converters

Design and testing of analog and mixed-signal (AMS) circuits is often regarded as representing significant bottlenecks in system-on-chip (SOC) design. Testing the analog and mixed-signal circuitry of a mixed-signal IC has become a difficult task. This is due to the fact that most analog and mixed signal circuits are tested by its functionality, which is both time consuming and expensive. Hence the importance of developing efficient and optimized test techniques dedicated to data converter products is evident. A novel built-in self-test scheme for testing on-chip digital to analog converters is proposed in this paper. This scheme employs an on-chip ramp signal generation for testing the converters. DACs considered for testing are R-2R, charge scaling and current steering DACs. The DAC architectures exhibit better performance with low INL and DNL of <0.5 LSB. The proposed BIST architecture is validated by testing all the DAC architectures with structural fault models. The proposed BIST provides average fault coverage of 95.22%. This paper presents the design of different DACs and the novel BIST architecture for testing the converters. All individual blocks in this paper are designed and simulated using Tspice with 0.18 mum CMOS technology.