Design of low power, high performance area efficient shannon based adder cell for neural network training

The design of a full-adder cell using multiplexing control input technique (MCIT) for the sum operation and the Shannon-based technique for carry operation were performed. The proposed adder cell can be applied to implement low power and high performance neural network training circuits. The hardware implementation of neural network will mainly consist of a multiplier circuit for the product term along with an adder circuit for the summation. The adder circuits are designed using TANNER EDA tools and the output parameters such as propagation delay, total chip area, and power dissipation are calculated from the simulated results and compared with MCIT based adder cell.