Author :
Kohama, Yoshinori ; Sugimori, Yasufumi ; Saito, Shotaro ; Hasegawa, Yohei ; Sano, Toru ; Kasuga, Kazutaka ; Yoshida, Yoichi ; Niitsu, Kiichi ; Miura, Noriyuki ; Amano, Hideharu ; Kuroda, Tadahiro
Author_Institution :
Department of Electronic Engineering and Electronics, Keio University, Yokohama, Japan
Abstract :
This paper presents homogeneous chip stacking to construct a scalable three-dimensional (3D) processor for the first time. Chips are connected by an inductive-coupling link. Power supply is delivered by conventional wire bonding. A prototype is developed by stacking four dynamically reconfigurable processor (DRP) chips in 90nm CMOS. Active Si area for the vertical link at 7.2Gb/s/chip is 0.031 mm2. Average execution time is reduced to 31% compared to that using one chip.
