Title :
A 21-Gb/s 87-mW transceiver with FFE/DFE/linear equalizer in 65-nm CMOS technology
Author :
Wang, Huaide ; Lee, Chao-Cheng ; Lee, An-Ming ; Lee, Jri
Author_Institution :
National Taiwan University, Taipei, Taiwan
Abstract :
This paper presents an ultra low-power transceiver for 20-Gb/s backplane communications. Incorporating half-rate, power-saving transmitter and full-rate, high-speed receiver with 2-stage equalization, this work achieves 21 Gb/s with BER≪10−12 over a 40-cm (16-inch) regular FR4 channel, while consuming a total power of only 87 mW from a 1.2-V supply.
Keywords :
Backplanes; Bandwidth; Bit error rate; CMOS technology; Clocks; Decision feedback equalizers; Inductors; Latches; Transceivers; Transmitters;
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
