Title :
Self-calibrating transceiver for source synchronous clocking system with on-chip TDR and swing level control scheme
Author :
Jang, Young-Chan ; Park, Joon-Young ; Shin, Sungcheol ; Choi, Hundae ; Lee, Kyongsu ; Woo, Byungsuk ; Park, Hwanwook ; Kim, Woo-Seop ; Choi, Youngdon ; Kim, Jaekwan ; Kim, Hyun-Kyung ; Kim, Jayoung ; Lim, Suyoun ; Chung, Su-Jin ; Kim, Sora ; Yoo, Jeihwan
Author_Institution :
ATD team, Memory Division, Samsung Electronics Co., LTD, San#16 Banwol-Dong Hwasung-City, Gyeonggi-Do, Korea
Abstract :
A transceiver chip with per-pin de-skew and read latency detection scheme utilizing on-chip TDR was implemented in 60nm DRAM process for the interface with source synchronous clock system. Without multi-phase clock, each time skew between Strobe and 16 Data was corrected within 0.028UI at 1.6-Gb/s data rate. Also, the jitter reduction of 50% was measured with swing-level controlled voltage-mode driver in the absence of destination termination at 1.6-Gb/s.
Keywords :
Clocks; Delay effects; Delay estimation; Delay lines; Gas detectors; Level control; Signal generators; System-on-a-chip; Timing; Transceivers; TDR; driver; read latency; time skew; transceiver;
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
