DocumentCode :
497964
Title :
A self-background calibrated 6b 2.7GS/s ADC with cascade-calibrated folding-interpolating architecture
Author :
Nakajima, Yuji ; Sakaguchi, Akemi ; Ohkido, Toshio ; Matsumoto, Tetsuya ; Yotsuyanagi, Michio
Author_Institution :
Core Development Division, NEC Electronics Corporation, Kawasaki, Kanagawa, 211-8668, Japan
fYear :
2009
fDate :
16-18 June 2009
Firstpage :
266
Lastpage :
267
Abstract :
We have developed a 6b 2.7GS/s Folding ADC with on-chip self-background calibration in 90nm CMOS. This is the first report of a successful background-calibrated ADC with a sampling rate of multi GHz. The algorithm enabled us to realize a system robust against environmental and process variation. To minimize the power consumption, a cascaded-calibration architecture was developed. The ADC dissipates 50mW at 2.7GS/s from a 1.0V supply. The figure of merit is 0.47pJ/conversion-step, which is the best reported value for multi-GHz ADCs with a resolution of 6bit or more.
Keywords :
Calibration; Circuits; Degradation; Electronic mail; National electric code; Power dissipation; Robustness; Sampling methods; System-on-a-chip; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
Type :
conf
Filename :
5205315
Link To Document :
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