• DocumentCode
    497965
  • Title

    A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS

  • Author

    Chung, Hayun ; Rylyakov, Alexander ; Deniz, Zeynep Toprak ; Bulzacchelli, John ; Wei, Gu-Yeon ; Friedman, Daniel

  • Author_Institution
    Harvard University, Cambridge, MA, England
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    268
  • Lastpage
    269
  • Abstract
    A 7.5-GS/s 4.5-bit analog-to-digital converter (ADC) in 65nm CMOS is presented. A two-stage track-and-hold (TAH) with clock duty cycle control reduces bandwidth requirements on the slow TAH output to enable high sampling rates with low power consumption. The 7.5-GS/s flash ADC consumes 52-mW and occupies 0.01-mm2. Clock duty cycle control improves ENOB from 3.5 to 3.8 with an input sinusoid at the Nyquist frequency.
  • Keywords
    Bandwidth; Calibration; Clocks; Communication system control; Energy consumption; Frequency; Oscilloscopes; Sampling methods; Switches; Topology; ADC; clock duty cycle control; high sampling rate; low power; two-stage track and hold;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205316
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497965